The present invention relates to a semiconductor Hall sensor, and more particularly to pattern geometry of a semiconductor Hall sensor.
Conventionally, semiconductor Hall sensors are widely used as rotating position detecting sensors of drive motors for VTRs, floppies (registered trademark) and CD-ROMs, or as potentiometers and gear sensors. As their magneto-sensitive films, are used InSb (indium antimonide) with high mobility and sensitivity, and GaAs (gallium arsenide) with large energy bandgap width and good temperature characteristic.
The semiconductor Hall sensor is one of the magnetic sensors, which has a characteristic of producing a Hall output voltage proportional to magnetic flux density in the direction perpendicular to a magneto-sensitive plane. Accordingly, the Hall output voltage should be zero when no magnetic field is present. However, in actuality the semiconductor Hall sensor can sometimes generate the Hall output voltage when applied with an input voltage even without the magnetic field. The voltage is called an unbalanced voltage (Vu).
The unbalanced voltage, which constitutes DC noise superimposed on the Hall output voltage, causes measuring error of the semiconductor Hall sensor. In addition, there are some cases where Si integrated circuit must be used to correct the unbalanced voltage in order to zero the Hall output voltage when no magnetic field is present, which presents a problem of cost and size.
FIG. 11 is a cross-sectional view showing a structure of a conventional semiconductor Hall sensor using a semi-insulating GaAs substrate. On the top surface of a semi-insulating GaAs substrate 11, selective ion implantation of Si or the like is carried out, or a magneto-sensitive film 12 composed of InSb, InAs (indium arsenide) or GaAs is formed by MBE (molecular beam epitaxy) or MOVPE (metal organic vapor phase epitaxy). Then, it is processed to a desired pattern by photolithography. Subsequently, an inorganic protective film 14 composed of SiO2 or SiN and internal electrodes 13 for passing a current are formed on the magneto-sensitive film 12, followed by dicing and die bonding. Then, wires 17 are connected to the electrodes 13, followed by molding with a resin 16. In FIG. 11, the reference numeral 15 designates a lead frame.
As described above, the magneto-sensitive pattern of the semiconductor Hall sensor is formed by patterning the magneto-sensitive film by the photolithography, followed by etching. The unbalanced voltage usually occurs because of geometric unbalance of a device geometry, which is produced during the patterning of the semiconductor Hall sensor. A leading cause thereof is that the pattern of the semiconductor Hall sensor drawn on the mask pattern is not in perfect agreement with the pattern of the actually fabricated semiconductor Hall sensor because of etching accuracy and the like.
To solve the problem, Japanese Patent Application Laid-open No. 1-298354, for example, discloses a method of chamfering four concave corners of a cross-shaped Hall device pattern (see, FIG. 8).
FIG. 2 is a diagram showing a pattern of a conventional semiconductor Hall sensor. At concave corners of a cross-shaped pattern 21, an input terminal side pattern forms a right angle of 90 degrees with an output terminal side pattern. The pattern of the semiconductor Hall sensor uses vertical electrodes as input side terminals, and horizontal electrodes as output side terminals.
Here, the length and width of the input terminal side pattern are denoted by L1 and W1, and the length and width of the output terminal side pattern are denoted by L2 and W2. More strictly, L1 and L2 are pattern distances of the semiconductor Hall sensor pattern across the electrodes, and W1 and W2 are defined as a greater one of the pattern width of the semiconductor Hall sensor and the pattern width of portions of the semiconductor Hall sensor contacting the electrodes.
Besides the chamfering, a method is known of reducing the unbalanced voltage by varying the ratio L/W of the length L and width W of the cross-shaped semiconductor Hall sensor pattern (in this example, it has a symmetric input/output pattern. Namely, L1=L2=L, W1=W2=W).
Generally, the unbalanced voltage generally reduces with an increase in L/W. However, an increasing L/W causes a new problem of increasing the size of the semiconductor Hall sensor. In addition, an increase in the L/W reduces the sensitivity (the output voltage under a specified magnetic flux density) of the semiconductor Hall sensor, which also presents a problem. In this method, since the rate of reduction of the unbalanced voltage is greater than that of the sensitivity, the signal-to-noise ratio is on the decrease, which means that the method is not suitable for a high accuracy measurement. Consequently, it is not a decisive method of reducing the unbalanced voltage.
Furthermore, the GaAs semiconductor Hall sensor or the like has a problem of a poor resistance to electrostatic as compared with the Si-composed integrated circuit (IC). The electric field takes a maximum value at concave corners of the pattern of the cross-shaped semiconductor Hall sensor. Thus, it is thought that the current concentrates to the concave corners, thereby causing a problem of destroying the device. The foregoing method disclosed in Japanese Patent Application Laid-open No. 1-298354 is effective for rather inaccurate etching like wet etching that is isotropic. However, dry etching with high anisotropy has been developed recently which utilizes ion milling or ECR (electron cyclotron resonance), thereby improving the etching accuracy. As a result, nearly ideal etching becomes possible, and hence the device with an almost identical geometry to the mask pattern can be formed. Therefore it is necessary to consider the pattern of the semiconductor Hall sensor capable of reducing the unbalanced voltage not empirically but theoretically.
The present invention is implemented in view of the foregoing problems. Therefore an object of the present invention is to provide a semiconductor Hall sensor capable of reducing the unbalanced voltage, and the measuring error resulting from the unbalanced voltage, and to improve the resistance to electrostatic.
The inventor of the present invention studied a pattern of the semiconductor Hall sensor that can reduce the unbalanced voltage through a simulation analysis and semiconductor Hall sensor prototypes. As a result of the simulation analysis, it was found theoretically that when the pattern of the semiconductor Hall sensor had defects or unbalance, the pattern of the semiconductor Hall sensor described in the foregoing Japanese Patent Application Laid-open No. 1-298354 with the chamfers increased the unbalanced voltage as compared with an ordinary cross-shaped Hall sensor pattern. The results will be described later in a comparative example 1.
Furthermore, the inventor of the present invention found patterns of the semiconductor Hall sensor, which were able to reduce the unbalanced voltage as compared with the conventional cross-shaped pattern or the pattern with the chamfers. In addition, inventor founds that the patterns of the semiconductor Hall sensor improved the resistance to electrostatic as well, thereby accomplishing the present invention.
To accomplish the objects of the present invention, according to a first aspect of the present invention, there is provided a semiconductor Hall sensor having a cross-shaped pattern that includes an input side pattern with a length and width of L1 and W1, and an output side pattern with a length and width of L2 and W2, the semiconductor Hall sensor being characterized in that: a film thickness, impurity concentration, the length L1 and width W1 of the input side pattern and the length L2 and width W2 of the output side pattern are maintained; and at least one of a resistance across input side terminals and a resistance across output side terminals is made 1.25 to 2.75 times a resistance of a cross-shaped pattern consisting of a rectangle with the length L1 and width W1 serving as the input side pattern, and a rectangle with the length L2 and width W2 serving as the output side pattern.
Thus placing the resistances of the input side pattern and output side pattern within the foregoing range can improve its characteristic by a few tens of percent as compared with the cross-shaped pattern without cutouts, when evaluated in terms of S/N, one of the most important characteristics of the Hall device.
In a range less than 1.25 times, the reduction effect of the unbalanced voltage is insufficient. In addition, when it is greater than 2.75 times, although the reduction in the unbalanced voltage is large, the S/N is deteriorated because of the reduction in signal component. As a result, the resistance is preferably in the range of 1.25 to 2.75 times.
According to a second aspect of the present invention, there is provided a semiconductor Hall sensor having a cross-shaped pattern that includes an input side pattern with a length and width of L1 and W1, and an output side pattern with a length and width of L2 and W2, the semiconductor Hall sensor comprising: at least one type of cutouts at consecutive two or four concave corners among four concave corners of a cross-shaped semiconductor Hall sensor, the cutouts having a geometry of one of a square, polygon, circle, ellipse and a combination of these forms, wherein the semiconductor Hall sensor is characterized in that: a film thickness, impurity concentration, the length L1 and width W1 of the input side pattern and the length L2 and width W2 of the output side pattern are maintained; and at least one of a resistance across input side terminals and a resistance across output side terminals is 1.25 to 2.75times a resistance of a cross-shaped pattern consisting of a rectangle with the length L1 and width W1 serving as the input side pattern, and a rectangle with the length L2 and width W2 serving as the output side pattern.
More preferably, both the resistance across the input side terminals and the resistance across the output side terminals may be 1.5 to 2.5 times the resistance of the cross-shaped pattern consisting of the rectangle with the length L1 and width W1 serving as the input side pattern, and the rectangle with the length L2 and width W2 serving as the output side pattern.
The foregoing range can improve the S/N of the Hall sensor by 30% or more. This makes it possible to suppress the characteristic variations to the same level achieved when a canceling circuit for suppressing the characteristic variations of the Hall IC is used, without using the canceling circuit of the unbalanced voltage. In addition, the resistance to electrostatic is improved markedly.
More preferably, the consecutive two or four concave corners of the four concave corners of the cross-shaped pattern may have an acute angle at an intersection of the input terminal side pattern and the output terminal side pattern of the cross-shaped pattern.
As a method of calculating the resistance of pattern geometry, anelectrostatic field analysis using a finite-element method is effective. The resistance can s be calculated by modeling the device geometry, analyzing the state that passes the constant current across the input or output terminals, calculating the voltage drop occurring at the time, and dividing the voltage drop by the amount of the current (Ohm""s law).